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CXD3606R
Timing Generator for Frame Readout CCD Image Sensor
Description The CXD3606R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX412 CCD image sensor. Features * Base oscillation frequency 45MHz * Electronic shutter function * Supports draft (sextuple speed) / AF (auto focus) drive * Horizontal driver for CCD image sensor * Vertical driver for CCD image sensor Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX412 (Type 1/1.8, 3240K pixels) 48 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.3 to +7.0 V VL -10.0 to VSS V VH VL - 0.3 to +26.0 V * Input voltage VI VSS - 0.3 to VDD + 0.3 V * Output voltage VO1 VSS - 0.3 to VDD + 0.3 V VO2 VL - 0.3 to VSS + 0.3 V VO3 VL - 0.3 to VH + 0.3 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDDb 3.0 to 5.25 VDDa, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL -7.0 to -8.0 * Operating temperature Topr -20 to +75
Pin Configuration
MCKO OSCO OSCI VDD5 VSS6 CKO SEN SCK CKI SSI HD VD
V V V V V C
36 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 37 38 39 40 41 42 43 44 45 46 47 48 1 VSS1
35
34
33
32
31
30
29
28
27
26
25 24 VSS5 23 ADCLK 22 OBCLP 21 VSS4 20 CLPDM 19 PBLK 18 XRS 17 XSHD 16 XSHP 15 VDD4 14 VDD3 13 H2
Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
2 RST
3 SNCSL
4 ID/EXP
5 WEN
6 SSGSL
7 VDD1
8 VDD2
9 RG
10 VSS2
11 VSS3
12 H1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E01216-PS
CXD3606R
Block Diagram
XSHD
XSHP
VDD3
VDD2
VDD4
14 12 13 11 OSCI OSCO 28 27
8
9
10
15 16 17 18 21 23
XRS
RG
H1
H2
ADCLK
VSS3
VSS2
VSS4
19 PBLK CKI 26 Pulse Generator CKO 25 MCKO 30 1/2 20 CLPDM 22 OBCLP 24 VSS5 4 5 ID/EXP WEN
SNCSL
3
Selector
Latch
41 V1A 43 V1B
SSI 31 SCK 32 SEN 33 Selector SSGSL 6 SSG V Driver Register
39 V2 44 V3A 46 V3B 40 V4 47 SUB 42 VH 38 VM 45 VL 7 VDD1 29 VDD5 1 VSS1 36 VSS6 35 HD 34 VD
RST
2
TEST1 37 TEST2 48
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CXD3606R
Pin Description Pin No. 1 2 Symbol VSS1 RST I/O -- I GND Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/protective diode on power supply side Control input used to switch sync system. High: CKI sync, Low: MCKO sync With pull-down resistor Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID) Memory write timing pulse output Internal SSG enable. High: Internal SSG valid, Low: External sync valid. With pull-down resistor 3.3V power supply. (Power supply for common logic block) 3.3V power supply. (Power supply for RG) CCD reset gate pulse output GND GND CCD horizontal register clock output CCD horizontal register clock output 3.3 to 5.0V power supply. (Power supply for H1/H2) 3.3V power supply. (Power supply for CDS) CCD precharge level sample-and-hold pulse output CCD data level sample-and-hold pulse output Sample-and-hold pulse output for analog/digital conversion phase alignment Pulse output for horizontal and vertical blanking period pulse cleaning CCD dummy signal clamp pulse output GND CCD optical black signal clamp pulse output The horizontal/vertical OB pattern can be changed using the serial interface data. Clock output for analog/digital conversion IC Logical phase adjustment possible using the serial interface data GND Inverter output Inverter input Inverter output for oscillation. When not used, leave open or connect a capacitor. Inverter input for oscillation. When not used, fix low. 3.3V power supply. (Power supply for common logic block) Description
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
SNCSL ID/EXP WEN SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5 CKO CKI OSCO OSCI VDD5
I O O I -- -- O -- -- O O -- -- O O O O O -- O O -- O I O I --
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CXD3606R
Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol MCKO SSI SCK SEN VD HD VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2
I/O O I I I I/O I/O -- I -- O O O -- O O -- O O I
Description System clock output for signal processing IC Serial interface data input for internal mode settings. Schmitt trigger input/protective diode on power supply side Serial interface clock input for internal mode settings. Schmitt trigger input/protective diode on power supply side Serial interface strobe input for internal mode settings. Schmitt trigger input/protective diode on power supply side Vertical sync signal input/output Horizontal sync signal input/output GND IC test pin 1; normally fixed to GND. GND (GND for vertical driver) CCD vertical register clock output CCD vertical register clock output CCD vertical register clock output 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output CCD vertical register clock output -7.5V power supply. (Power supply for vertical driver) CCD vertical register clock output CCD electronic shutter pulse output IC test pin 2; normally fixed GND. With pull-down registor With pull-down resistor
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CXD3606R
Electrical Characteristics DC Characteristics Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 Input voltage 11 Input voltage 22 VDD2 VDD3 VDD4 VDD1, VDD5 RST, SSI, SCK, SEN TEST1, TEST2, SNCSL, SSGSL Pins Symbol VDDa VDDb VDDc VDDd Vt+ Vt- VIH1 VIL1 VIH2 Input/output voltage VD, HD VIL2 VOH1 VOL1 Output voltage 1 H1, H2 VOH2 VOL2 VOH3 VOL3 Feed current where IOH = -1.2 mA Pull-in current where IOL = 2.4mA Feed current where IOH = -22.0mA Pull-in current where IOL = 14.4mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -2.4mA Pull-in current where IOL = 4.8mA V1A/B, V2, V3A/B, V4 = -8.25V V1A/B, V2, V3A/B, V4 = -0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = -8.25V SUB = 14.75V 5.4 -4.0 5.0 -7.2 10.0 -5.0 VDDd - 0.8 0.4 VDDd - 0.8 0.4 VDDd - 0.8 0.4 VDDc - 0.8 0.4 VDDa - 0.8 0.4 VDDb - 0.8 0.4 VDDd - 0.8 0.4 0.8VDDd 0.2VDDd 0.7VDDd 0.2VDDd (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd 0.2VDDd Typ. 3.3 3.3 3.3 3.3 Max. 3.6 5.25 3.6 3.6 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA
Output voltage 2
RG
Output voltage 3
XSHP, XSHD, VOH4 XRS, PBLK, OBCLP, CLPDM, VOL4 ADCLK CKO VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL
Output voltage 4
Output voltage 5
MCKO ID/EXP, WEN
Output voltage 6
Output current 1
V1A, V1B, V3A, V3B, V2, V4
IOM1 IOM2 IOH
Output current 2
SUB
IOSL IOSH
1 These input pins are Schmitt trigger inputs, and have a protective diode on the power supply side in the IC. Therefore, they do not support 5V input. 2 This input pin is with pull-down registor in the IC. Note) The above table indicates the condition for 3.3V drive. -5-
CXD3606R
Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Pins OSCI OSCI Symbol LVth VIH VIL VOH VOL RFB f
(Within the recommended operating conditions) Conditions Min. Typ. VDDd/2 0.7VDDd 0.3VDDd Max. Unit V V V V 0.4 500k 20 2M 5M 50 V MHz
Output voltage Feedback resistor Oscillation frequency
OSCO OSCI, OSCO OSCI, OSCO
Feed current where IOH = -3.6mA VDDd - 0.8 Pull-in current where IOL = 2.4mA VIN = VDDd or VSS
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = -7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V
Notes) 1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1F or more) between each power supply pin (VH, VL) and GND. 3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. -6-
CXD3606R
Switching Waveforms
TTMH 90%
TTHM VH 90%
V1A (V1B, V3A, V3B)
TTLM
10% 90%
10% 90%
TTML
VM
10%
10%
VL
TTLM 90% V2 (V4) 10% 90%
TTML
VM
10%
VL
TTLH 90% 90%
TTHL
VH
SUB
10%
10% VL
Waveform Noise
VM VCMH VCML
VCLH VCLL VL
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CXD3606R
Measurement Circuit
Serial interface data CKI C6
VD HD +3.3V -7.5V +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 37 R1 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 C2 C1 C2 R1 C2 R2 C3 C1 C2 C2 C1 C2 C2 R1 38 39 40 41 42 43 44 R1 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 CXD3606R 24 23 22 21 20 19 18 17 16 15 14 13 C5 C6 C6 C6 C6 C6 C6 C6 C6
C2 C2
R1
C4
C5
C1 3300pF R1 30
C2 560pF R2 10
C3 820pF
C4 8pF
C5 215pF
C6 10pF
-8-
CXD3606R
AC Characteristics AC characteristics between the serial interface clocks
0.8VDDd SSI SCK SEN SEN ts2 0.2VDDd 0.8VDDd 0.2VDDd ts1 0.2VDDd ts3 0.8VDDd
th1
(Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns
ts1 th1 ts2 ts3
Serial interface clock internal loading characteristics (1)
Example: During frame mode VD HD
V1A Enlarged view HD
0.2VDDd
V1A ts1 SEN 0.8VDDd 0.2VDDd th1
Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HD SEN hold time, activated by the falling edge of HD -9- Min. 0 113 Typ. Max. Unit ns s
ts1 th1
CXD3606R
Serial interface clock internal loading characteristics (2)
Example: During frame mode VD HD Enlarged view
VD HD
0.2VDDd
ts1 SEN 0.8VDDd
th1 0.2VDDd
Be sure to maintain a constantly high SEN logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of VD SEN hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns
ts1 th1
Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3606R at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3606R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDd
Output signal tpdPULSE
(Within the recommended operating conditions) Symbol Definition Min. 15 Typ. Max. 100 Unit ns
tpdPULSE Output signal delay, activated by the rising edge of SEN
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CXD3606R
RST loading characteristics
RST
0.2VDDd tw1
0.2VDDd
(Within the recommended operating conditions) Symbol Definition RST pulse width Min. 28 Typ. Max. Unit ns
tw1
VD and HD phase characteristics
VD
0.2VDDd ts1 th1 0.2VDDd
0.2VDDd
HD
(Within the recommended operating conditions) Symbol Definition VD setup time, activated by the falling edge of HD VD hold time, activated by the falling edge of HD Min. 0 0 Typ. Max. Unit ns ns
ts1 th1
HD loading characteristics
HD
0.2VDDd ts1 th1 0.8VDDd
0.2VDDd
MCKO
MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition HD setup time, activated by the rising edge of MCKO HD hold time, activated by the rising edge of MCKO Min. 20 0 Typ. Max. Unit ns ns
ts1 th1
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CXD3606R
Output variation characteristics
MCKO
0.8VDDd
WEN, ID/EXP tpd1
WEN and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 25 Typ. Max. 70 Unit ns
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CXD3606R
Description of Operation Pulses output from the CXD3606R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS1 RST SNCSL ID/EXP WEN SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5 ACT ACT L L -- ACT ACT ACT ACT ACT L L L L L -- L L H ACT ACT ACT L L -- -- L L L L L ACT ACT ACT H H ACT L -- -- L L ACT ACT ACT ACT ACT ACT ACT ACT ACT L L ACT -- -- L ACT CAM SLP -- ACT ACT L L ACT L ACT L L ACT STB RST Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKO CKI OSCO OSCI VDD5 MCKO SSI SCK SEN VD1 HD1 VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 ACT ACT VH VH -- ACT ACT VH VH -- VH VH VL VL ACT ACT ACT VM VM VH -- VH VH VM VL ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT L L -- -- -- VM VM VH VM VL VM CAM ACT ACT ACT ACT SLP ACT ACT ACT ACT -- L ACT ACT ACT L L ACT DIS DIS DIS H H STB L ACT ACT ACT RST ACT ACT ACT ACT
1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45), respectively, in the controlled status.
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CXD3606R
Serial Interface Control The CXD3606R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN.
SSI SCK SEN
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
These are two categories of serial interface data : the CXD3606R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below.
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CXD3606R
Control Data Data D00 to D07 D08 D09 D10 to D12 D13 D14 D15 D16 to D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 to D47 FGOB EXP PTOB LDAD STB Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 0 0 0 All 0 0 0 All 0 1 0 All 0 All 0
10000001 Enabled Other values Disabled See D08 to D09 CTG.
CTG
Category switching
MODE SMD HTSG PTSG --
Drive mode switching Electronic shutter mode switching1 HTSG control switching1 Internal SSG function switching -- Wide OBCLP generation switching2 ID/EXP output switching OBCLP waveform pattern switching ADCLK logic phase adjustment Standby control
See D10 to D12 MODE. OFF OFF NTSC -- OFF ID ON ON PAL -- ON EXP
See D34 to D35 PTOB. See D36 to D37 LDAD. See D38 to D39 STB.
--
--
--
--
1 See D13 SMD. 2 See D32 FGOB.
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CXD3606R
Shutter Data Data D00 to D07 D08 D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 All 0
10000001 Enabled Other values Disabled See D08 to D09 CTG.
CTG
Category switching Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification
SVD
See D10 to D19 SVD.
SHD
See D20 to D31 SHD.
SPL
See D32 to D41 SPL.
--
--
--
--
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CXD3606R
Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD3606R by the serial interface, the CXD3606R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 D08 0 1 X Description of operation Loading to control data register Loading to shutter data register Test mode
Note that the CXD3606R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode] The CXD3606R drive mode can be switched as follows. However, the drive mode bits are located to the CXD3606R and reflected at the falling edge of VD. D12 0 0 0 0 1 1 D11 0 0 1 1 0 1 D10 0 1 0 1 X X Description of operation Draft mode (sextuple speed: default) Frame mode (A field readout) Frame mode (B field readout) Frame mode AF1 mode AF2 mode
Control data: D15 PTSG [Internal SSG output pattern] The CXD3606R internal SSG output pattern can be switched as follows. However, the internal SSG output pattern bits are loaded to the CXD3606R and reflected at the falling edge of VD. D15 0 1 Description of Operation NTSC equivalent pattern output PAL equivalent pattern output
VD period in each pattern is defined as follows. However, note that the HD period also changes according to the mode. Frame mode NTSC equivalent pattern PAL equivalent pattern 885H + 810ck 884H + 1104ck Draft mode AF1 mode AF2 mode 71H + 1384ck 85H + 1960ck
285H + 1455ck x 2 142H + 1384ck + 1383ck 342H + 2592ck 171H + 1296ck
See the Timing Charts for the actual operation. - 17 -
CXD3606R
Control data: D32 FGOB [Wide OBCLP generation] This controls wide OBCLP generation during the vertical OPB period. See the Timing Charts for the actual operation. The default is "OFF". D32 0 1 Description of operation Wide OBCLP generation OFF Wide OBCLP generation ON
Control data: D34 to D35 PTOB [OBCLP waveform pattern] This indicates the OBCLP waveform pattern. The default is "Normal". D35 0 0 1 1 D34 0 1 0 1 Waveform pattern (Normal) (Shifted rearward) (Shifted forward) (Wide)
Control data: D36 to D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is "90" relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment () 0 90 180 270
Control data : D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD3606R and control is applied immediately at the rising edge of SEN. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode
See the Pin Status Table for the pin status in each mode.
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CXD3606R
Control data/shutter data: [Electronic shutter] The CXD3606R realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 SMD. D13 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 X D30 0 1 D29 0 D28 1 D27 1 D26 1 C D25 0 D24 0 D23 0 D22 0 3 D21 1 LSB D20 1 SHD is expressed as 1C3h .
[Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h SVD 3FFh) Number of horizontal periods specification (000h SHD 7FFh) Vertical period specification for high-speed shutter operation (000h SPL 3FFh)
Note) The bit data definition area is assured in terms of the CXD3606R functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVD + {(number of HD per 1V) - (SHD + 1)} Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses - 1). - 19 -
CXD3606R
VD
SHD
SVD
V1A SUB WEN EXP SMD SVD SHD 1 002h 10Fh 1 000h 050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL 000 VD SHD V1A SUB WEN EXP SMD SPL SVD SHD 1 001h 002h 10Fh 1 000h 000h 0A3h 001 SVD 002
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. At this time, even if SPL > SVD is set, operation conforms to the state when SPL = SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa.
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CXD3606R
[HTSG control mode] This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG. When control is applied, V pulse modulation does not occur during the readout period, and only normal V transfer is performed. D14 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode
VD
V1A SUB Vck WEN EXP HTSG SMD 0 1 1 0 0 1
Exposure time
[EXP pulse] The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. In draft mode, the transition point is midpoint value (1443ck) of the last SUB pulse falling edge and each V1A/B and V3A/B ternary output falling edge. When there is no SUB pulse, the later ternary output falling edge (1538ck) is used. In frame mode, the transition point is the last SUB pulse falling edge, and each V1A/B and V3A/B ternary level output falling edge (1348ck). When there is no SUB pulse, the V pulse modulation falling edge (1386ck) immediately after the ternary output is used. In addition, switching from the ID pulse to the EXP pulse is performed at the ID reset timing (the ID transition point during the horizontal period of each V1A/B and V3A/B ternary level output), and the EXP pulse is reset low at this point. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation.
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Chart-1
Frame mode
A Field B Field
Vertical Direction Timing Chart
* ICX412
MODE
Applicable CCD image sensor
VD
886 1 96 101 95 877 886 1 101
877
HD
SUB C
High-speed sweep block
A C High-speed sweep block
B
V1A
V1B
V2
V3A
1542
1544
1546
1548
1550
1543
1545
1547
CCD OUT
PBLK
OBCLP
Wide OBCLP
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. The high-speed sweep block is fixed to 1560 stages. VD of this chart is NTSC equivalent pattern (885H + 810ck units). For PAL equivalent pattern, it is 884H + 1104ck units.
1549
- 22 -
1 3 5 7 1 3 5 7 9 11
V3B
V4
2 4 6 8 2 4 6 8 10
CXD3606R
Chart-2
Draft mode
* ICX412
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
VD
287 1 2 260 287 1 2
260
HD
SUB D D
V1A
V1B
V2
V3A
V3B
1525 1527
1532 1534
1544 1546
1525 1527
1532 1534
1537 1539
1549
1537 1539
1544 1546
PBLK
OBCLP
Wide OBCLP
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. VD of this chart is NTSC equivalent pattern (285H + 1455ck + 1455ck units). For PAL equivalent pattern, it is 342H + 2592ck units.
1549
- 23 -
6 3 10 15 22 27 30 4 1 8 13 20 25 28
V4
6 3 10 15 22 27 30 4 1 8 13 20 25 28
CCD OUT
CXD3606R
Chart-3
AF1 mode
* ICX412
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
VD
144 14 2 131 144 2 14
131
HD
SUB E
Frame shift block Frame shift block
E
High-speed sweep block
D
E
High-speed sweep block
D
E
V1A
V1B
V2
V3A
421 423
428 430
433 435
440 442
421 423
428 430
433 435
1112 1114
1117 1119
1112 1114
PBLK
OBCLP
Wide OBCLP
CLPDM
ID/EXP
WEN

CXD3606R
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern it is 171H + 1296ck units, and the high-speed sweep block starts from 159H.
1117 1119
440 442
- 24 -
6 4
V3B
V4
6 4
CCD OUT
Chart-4
AF2 mode
* ICX412
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
VD
2 21 54 72 2 21
54
72
HD
SUB E
Frame shift block
E
High-speed sweep block
D
E
High-speed sweep block
D
E Frame shift block
V1A
V1B
V2
V3A
862
867
860 862
673 675
680 682
685 687
692 694
865 867
673 675
680 682
685 687
860
PBLK
OBCLP
Wide OBCLP
CLPDM
ID/EXP
WEN

865
692 694
- 25 -
6 4
V3B
V4
6 4
CCD OUT
CXD3606R
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (71H + 1384ck units). For PAL equivalent pattern, it is 85H + 1960ck units, and the high-speed sweep block starts from 68H. However, in this case the frame rate for NTSC equivalent pattern is 0.5ck longer than for 1/120s.
Chart-5
Frame mode
* ICX412
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
(2544) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
428 456/460/464
4
52
H1
H2
162 238 124 200 120 454 390 314 352 276
V1A/B
V2
V3A/B
V4
52
SUB
- 26 -
124 124
52
PBLK
16
42
OBCLP (1)
8
34
OBCLP (2)
24
50
OBCLP (3)
458 430 454
8
50
OBCLP (4)
50
OBCLP (wide)
CLPDM
ID/EXP
WEN

CXD3606R
The HD of this chart indicates the actual CXD3606R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1. OBCLP (wide) is output at the above timing at the position indicated in Chart-1.
Chart-6
Draft mode, AF1 mode, AF2 mode
* ICX412
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
(2624) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
508 536/540/544
4
52
H1
H2
140 172 124 156 120 534 236 284 364 204 252 332 380 412 220 300 348 428 460 492 188 268 316 396 444 476
V1A/B
V2
V3A/B
V4
52
SUB
52
- 27 -
124 124
PBLK
16
42
OBCLP (1)
8
34
OBCLP (2)
24
50
OBCLP (3)
538 510 534
8
50
OBCLP (4)
50
OBCLP (wide)
CLPDM
ID/EXP
WEN

The HD of this chart indicates the actual CXD3606R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2,3 and 4. OBCLP (wide) is output at the above timing at the position indicated in Chart-2,3 and 4.
CXD3606R
Chart-7
Frame mode
* ICX412
Horizontal Direction Timing Chart (High-speed sweep: C)
MODE
Applicable CCD image sensor
(2544) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
428 456/460/464
4
52
H1
H2
128 166 128 166 242 318 394 204 280 356 242 318 394 432 470 204 280 356 432 470 508 546 508 546
52
V1A/B
90
V2
52
V3A/B
90
V4 #1
120
#2
#3
#4
- 28 -
52
SUB
PBLK
OBCLP
CLPDM
ID/EXP
WEN

The HD of this chart indicates the actual CXD3606R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 98H 580ck (#1560).
CXD3606R
Chart-8
AF1 mode, AF2 mode
* ICX412
Horizontal Direction Timing Chart (Frame shift, high-speed sweep: E)
MODE
Applicable CCD image sensor
(2624) 0 100 150 200 250 300 350 400 450 500
50
550
HD
MCKO
508 536/540/544
4
52
H1
H2
116 100 132 164 242 292 340 180 260 308 388 420 148 228 276 356 404 436 468 196 244 324 372 452 484 516 548 500 532
68
V1A/B
V2
52
V3A/B
84
V4 #1
120
#2
52
- 29 -
124
SUB
52
PBLK
16
42
OBCLP
CLPDM
ID/EXP
WEN

The HD of this chart indicates the actual CXD3606R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. PBLK, OBCLP, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3 and 4. Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 11H 2548ck (#68) in AF1 mode and 18H 308ck (#110) in AF2 mode. In addition, high-speed sweep is performed up to 141H 2612ck (#75) in AF1 mode and 70H 2612ck (#116) in AF2 mode.
CXD3606R
Chart-9
Frame mode
* ICX412
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
1196
1234
1272
1310
1348
1386
124
162
200
238
276
314
352
(2544) 0 390
(2544) 0
HD A
[A Field]
V1A
V1B
V2
V3A
V3B
V4 B
- 30 -
[B Field]
V1A
V1B
V2
V3A
V3B
V4
The HD of this chart indicates the actual CXD3606R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
CXD3606R
Chart-10
Draft mode, AF1 mode, AF2 mode
* ICX412
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
1158
1196
1234
1272
1310
1348
1386
1424
1462
1500
1538
1576 1592 1608 1624 1640 1656 1672 1688
(2624) 0
(2544) 0
HD D
V1A
V1B
V2
V3A
- 31 -
V3B
V4
The HD of this chart indicates the actual CXD3606R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
124 140 156 172 188 204 220 236 252 268 284 300 316 332 348 364 380 396 412 428 444 460 476 492
CXD3606R
Chart-11
* ICX412
High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
HD
HD'
CKI
CKO
ADCLK
52 428/508
1
MCKO
- 32 -
H1
H2
RG
XSHP
XSHD
XRS
HD' of this chart indicates the HD which is the actual CXD3606R load timing. The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. The logical phase of ADCLK can be specified by the serial interface data. CXD3606R
Chart-12
Draft Frame Draft
* ICX412
Vertical Direction Sequence Chart
MODE
Applicable CCD image sensor
VD
V1A
V1B
V2
V3A
V3B
- 33 -
Close C B E 0 1 050h 3 0 000h 0 1 050h 050h 1 0 C D E
V4
SUB Open F E 3 0 000h 0 1 050h F 0 1 050h
Mechanical shutter
Exposure time
A
B
CCD OUT
A
MODE
0
0
SMD
1
1
SHD
050h
050h

This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD3606R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data is not the same.
CXD3606R
CXD3606R
Application Circuit Block diagram
CCD ICX412
CCD OUT
CDS/ADC Block
Digital OUT
CLPDM
OBCLP
H1 H2 RG V1A V1B V2 V3A V3B V4 SUB
16 17 18 19 20 22 23 12 13 9 25 41 43 39 44 46 40 47 26 27 28 37 48 31 32 33 V-Dr TG CXD3606R 30 34 SSG 35 2 3 6 4 5 ID/EXP WEN CKO MCKO VD HD RST SNCSL SSGSL Signal Processor Block
CKI OSCO
SSI
ADCLK SCK SEN
XSHD
XSHP
TEST1
PBLK
XRS
TEST2
OSCI
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on Of the three -7.5V, +15.0V, +3.3V power supplies, be sure to start up the -7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20% 0V 20%
t2 t2 t1 -7.5V
- 34 -
CXD3606R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.5 0.2
S
0.18 0.03
0 to 10
0.5 0.2
DETAIL B: PALLADIUM DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 P-LQFP48-7x7-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g
- 35 -
0.127 0.04
Sony Corporation

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